• 2+ years’ experience in STA/Synthesis
• Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.
• Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.
• Hands-on the DMSA flow to fix pre and post STA timing.
• Knowledge on the Timing closure on Sub system level & Block level and Chip level.
• Knowledge on Writing Manual ECO’s to fix timing violations and DRC’s.
• Knowledge on constraint development.
• Good Knowledge of TCL scripting and UNIX env.