Posted 3 months ago
- Expertise in physical verification of SoC/Full-chip-level and/or block-level DRC, Experience and understanding of all phases of the IC design process from RTL->GDS2
- LVS, ERC/PERC, DFM, OPC, Tapeout process
- Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries
- Experience in developing sign-off methodology/flow to and supporting a larger team
- Experience in debugging LVS issues at chip-level with complex analog-mixed signal IPs
- Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
- Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components
- Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc.
- Experience with ERC rules, PERC rules, ESD rules has an added advantage
- EDA Tools: Cadence (Pegasus), Mentor (Calibre), Synopsys (ICV)
Job Features
| Job Code | ICD-PVE-019 |
| Qualification | B.E or M.Tech in Electronics / VLSI Engineering |
| Experience | 2-20 Years |