• Expertise in physical verification of SoC/Full-chip-level and/or block-level DRC, Experience and understanding of all phases of the IC design process from RTL->GDS2
• LVS, ERC/PERC, DFM, OPC, Tapeout process
• Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries
• Experience in developing sign-off methodology/flow to and supporting a larger team
• Experience in debugging LVS issues at chip-level with complex analog-mixed signal IPs
• Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
• Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components
• Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc.
• Experience with ERC rules, PERC rules, ESD rules has an added advantage
• EDA Tools: Cadence (Pegasus), Mentor (Calibre), Synopsys (ICV)

• Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context.
• Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies
• Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space.
• Good handle on IR/EM related issues in memory layouts.
• Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
• Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines.
• Experience & or strong interest in memory compilers developed.
• Excellent and demonstrated team player with ability to work with external customers and in cross functional teams.

Role Overview:

• Design and verify analog circuit IPs (building blocks) to meet functional and performance specifications.
• Translate customer requirements into precise design specifications and innovative solutions.
• Conduct feasibility studies to analyze and evaluate analog design concepts.

Key Responsibilities:

• Expertise in Mixed-Signal Circuit Design: PLLs, DLLs, CDRs, Transceivers, Clocking Circuits, Data Converters, LDOs, DC-DC Converters, High-Speed Circuits (USB, DDR, SerDes).
• Lead all aspects of analog design projects from concept through execution and delivery.
• Address technology and process challenges in porting designs across technology nodes.

Skills & Qualifications:

• 2+ years of experience in Analog Mixed-Signal IC design.
• Deep understanding of analog design principles and AMS verification.
• Strong communication skills and ability to collaborate with cross-functional teams.

• 2 + year experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence Virtuoso L/VXL and Calibre DRC/LVS is a must.
• SKILL/Perl scripting is a plus.
• Should have hands on experience of Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power, and area etc.,
• Ability to understand design constraints and implement high-quality layouts.
• Excellent verbal and written communication skills.

Roles Responsibilities

• Define micro architecture from datasheet or requirements document
• Do RTL-level design for any digital logic
• Perform module-level verification and lint checking
• Interact with verification engineers for test plan review, coverage debug

Skills, Qualification and Experience

• 2+years of experience in ASIC Design
• Strong hands-on experience with Verilog design
• Should be able to work independently once the design requirements are specified
• Knowledge of standard interfaces viz., AXI, AHB, Flash-Memory, OTP, I2C/SPI is a plus
• Knowledge of VP3, Perl, and EDA tools for LEC, Synthesis is a plus
• Must have good spoken and written communication skills
• Collaborate well in a team

• 2+ years’ experience in STA/Synthesis
• Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.
• Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.
• Hands-on the DMSA flow to fix pre and post STA timing.
• Knowledge on the Timing closure on Sub system level & Block level and Chip level.
• Knowledge on Writing Manual ECO’s to fix timing violations and DRC’s.
• Knowledge on constraint development.
• Good Knowledge of TCL scripting and UNIX env.

• 2+ years of experience in DFT domain
• Expertise in DFT methodologies - scan insertion, scan compression, boundary scan, and memory BIST
• Experience in DFT tools like Tessent, ATPG, MBIST, and JTAG
• Experience in the complete scan chain flow (ATPG, simulation, and test pattern generation) on complex SOCs
• Knowledge of STA, LEC, and physical design aspects related to DFT
• Experience in Shell/Perl/Tcl and other scripting languages
• Good communication skills and the ability to work well in a team environment

• Minimum 2+ Years of Experience in Physical Design
• Block Level P&R / Sub-system Level P&R/ Tile Level P&R.
• Experienced in Cadence (EDI) or Synopsys (ICC) and Mentor (Calibre) EDA Tools.
• Process node experience to be in the range of 40nm & below (i.e. 28 nm, 16 nm, 10
• nm,5nm,3nm).
• Responsible for full chip implementation of complex SoCs (RTL-to-GDSII)
• Good Leadership skills and people management skills.

• ASIC/SOC/IP/GLS Verification plan definition, testbench environment development in System Verilog/UVM
• Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level
• Support of assertion and coverage-driven methodology
• Develop test cases to verify functional operation of that the system level
• Experience in PCIe or NVMe or UFS or SATA or SAS or Ethernet or AXI or DDR protocols
• Communicate test progress, test results, and other relevant information to project lead
• Test any new software to ensure integration into company system meets functional requirements, system compliance, and technical specifications
• Analyse formal test results in order to discover and report any defects, bugs, errors, configuration issues, and interoperability flaws
• Code and functional coverage objects of different blocks
• Manage a team of verification engineers to perform the above tasks