Roles Responsibilities

• Define micro architecture from datasheet or requirements document
• Do RTL-level design for any digital logic
• Perform module-level verification and lint checking
• Interact with verification engineers for test plan review, coverage debug

Skills, Qualification and Experience

• 2+years of experience in ASIC Design
• Strong hands-on experience with Verilog design
• Should be able to work independently once the design requirements are specified
• Knowledge of standard interfaces viz., AXI, AHB, Flash-Memory, OTP, I2C/SPI is a plus
• Knowledge of VP3, Perl, and EDA tools for LEC, Synthesis is a plus
• Must have good spoken and written communication skills
• Collaborate well in a team